Electronic information handling or computer systems, whether large machines, microcomputers or small and simple digital processing devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes semiconductor memory devices.
Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Flash memory is often used where regular access to the data stored in the memory device is desired, but where such data is seldom changed. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory and are continually pushing for lower voltages and higher densities. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment also use flash memory as a medium to store data.
Conventional flash memory cells make use of a floating-gate transistor including a source region, a drain region, a floating-gate layer and a control-gate layer. In such devices, access operations are carried out by applying biases to each of these terminals. Write operations are generally carried out by channel hot-carrier injection. This process induces a flow of electrons between the source and the drain, and accelerates them toward a floating gate in response to a positive bias applied to the control gate. Read operations generally include sensing a current between the source and the drain, i.e., the MOSFET current, in response to a bias applied to the control gate. Erase operations are generally carried out through Fowler-Nordheim tunneling. This process may include electrically floating the drain region, grounding the source region, and applying a high negative voltage to the control-gate layer.
Another important form of semiconductor memory device includes a volatile memory called dynamic random access memory (DRAM). DRAM is often used where rapid access to the memory array is desired for both data input and data output. DRAM has faster access times than flash memory, but requires periodic refresh to avoid losing its data values. Typical DRAM configuration includes an array of memory cells placed at the intersection of word lines and bit lines. Each memory cell includes an access transistor, with the gate of each access transistor coupled to a word line. A first source/drain region of an access transistor is coupled to a bit line and a second source/drain region of the access transistor is coupled to a first plate of a capacitor. The data value is stored as a charge on the capacitor and the data value is sensed by charge sharing with the associated bit line and detecting the change to the bit-line potential as a result of the charge sharing. Computer applications typically use DRAM to store program instructions and other temporary data.
Prior to shipping, a manufacturer may test its semiconductor memory devices as part of a quality program to improve end-use reliability. One of the tests performed includes a write verify test. Generally, the write verify test is used to test the ability of the memory array to receive, retain and output data reliably. Such tests typically first involve writing a pattern of data, e.g., an input pattern of 1s (ones) and 0s (zeros), to the memory array. The memory array is subsequently accessed to sense and output the data stored in the memory array. The data is often output as a page of data containing two or more words with each word containing some number of bits. The output data is then compared to the pattern of data originally input to the memory array on a bit-by-bit basis, and generally one word at a time, by an arbitration circuit of a testing apparatus. If each bit of each word of the output data matches the corresponding bit of the input pattern, the device passes the test. A mismatch between any bit of any word of the output data and the input pattern is indicative of a device failure. These tests, while valuable to verify device reliability, are time consuming and expensive.
U.S. patent application Ser. No. 09/943,642 filed Aug. 30, 2001, titled “DATA COMPRESSION READ MODE FOR MEMORY TESTING” and published Aug. 29, 2002 as U.S. Patent Application Publication 2002/0118580 A1, describes a data compression test mode wherein reading one word of an output page provides an indication of the data values of the remaining words of the output page. In this manner, read time of a memory array having a repeating pattern can be reduced to a fraction of the time required to read every word of the array. Consequently, the time required for testing the ability of a memory device to accurately store data can be reduced. Such methods can reduce testing time generally by an order of magnitude, but as memory sizes become larger, still higher reductions in testing time are advantageous.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods of testing memory devices, circuits for implementing such test methods, and memory devices making use of such circuits and test methods.